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general description the MAX3886 2.488gbps/1.244gbps/622mbps cdrwith serdes (serializer/deserializer) is designed specifi- cally for low-cost optical network terminal (ont) appli- cations in gigabit passive optical network (gpon) and broadband passive optical network (bpon) fiber-to- the-home (ftth) systems. it provides g.984- and g.983-compliant clock and data recovery (cdr) for the continuous downstream data signal, with an integrated 4-bit serdes that has lvds parallel interfaces and cml serial interfaces. the serdes uses the recovered downstream clock for upstream serialization (loopback clock), providing opti- mum pon operation. the cdr frequency reference can be provided by a low-cost 19.44mhz smd-type crystal or external lvcmos source, and excellent jitter tolerance supports applications requiring fec. an inte- grated burst-enable signal path also simplifies high- performance upstream burst timing. this 3.3v ic is housed in a 8mm x 8mm, 56-lead thin qfn package and operates from -40? to +85?. applications bpon/gpon optical network terminal (ont) features ? 2.488gbps, 1.244gbps, and 622mbps clock anddata recovery ? meets g.984 and g.983 jitter requirements ? 4-bit serializer and 4-bit deserializer with loop-timed serialization ? cml serial i/o, lvds parallel i/o ? integrated reference oscillator uses 19.44mhzsmd crystal ? integrated upstream burst-enable signal path MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications ________________________________________________________________ maxim integrated products 1 ordering information 19-3103; rev 0; 12/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. evaluation kit available pin configuration appears at end of data sheet. part temp range pin- package pkg code MAX3886etn+ -40 c to +85 c 56 tqfn (8mm x 8mm) t5688-2 0.27 f rfck1 rfck2 sdi mvco mddr msym pcko pdo[3:0] pdi[3:0] pcki beni gnd lock v cc v cc cfil +3.3v +3.3v 19.4400mhz 2.488g +3.3v MAX3886 gpon cdr/serdes max3747/ max3748 lim amp frst ferr sdo beno 1.244g 870mhz video gpon optical network terminal (ont) 1310nm 1490nm pon 1550nm max3643/ max3656 ld driver max3654 video tia bidi triplexer pclk (311mhz) mac ic pdata (622mbps)pdata (311mbps) pclk (311mhz) burst enable slic voice 10/100 ethernet data typical application circuit downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 2 _______________________________________________________________________________________ absolute maximum ratings operating conditions stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage range (v cc ).................................-0.3v to +4.0v cml input voltage range (sdi )...............-0.3v to (v cc + 0.3v) cml output current (sdo , beno )............................... 22ma lvds input voltage range (pcki , pdi[3:0] , beni )......................-0.3v to (v cc + 0.3v) lvds output voltage range (rcko , pdo[3:0] , pcko ) ................-0.3v to (v cc + 0.3v) lvcmos input voltage range (msym, mddr, frst)............................-0.3v to (v cc + 0.3v) three-state input voltage range (mvco)...................................................-0.3v to (v cc + 0.3v) lvcmos output voltage range (lock, ferr) ........................................-0.3v to (v cc + 0.3v) voltage range at cfil, rfck1, rfck2, tp1, tp2, tp3, tp4 ...................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70 c) 56-pin tqfn (derate 47.6mw/ c above 70 c)..........3808mw operating junction temperature range ...........-55 c to +150 c storage temperature range .............................-55 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units operating temperature t a -40 +85 c power-supply voltage v cc 3.0 3.6 v downstream/upstream data rates see table 2 gbps reference frequency internal or external oscillator 19.4400 mhz crystal accuracy includes aging, temperature, and other contributors 250 ppm crystal esr fundamental type, at-strip cut 10 60 crystal drive 100 w crystal load capacitance on-chip parallel capacitance 18 p f reference clock input duty cycle when driven by an lvcmos clock source 40 60 % electrical characteristics(v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted. lvds outputs terminated 100 differential, cml inputs terminated 100 differential, cml outputs terminated 100 differential.) (note 1) parameter symbol conditions min typ max units supply current i cc 240 310 ma cdr/deserializer specifications mvco = 1 2488.32 mvco = open 1244.16 serial input data rate rate mvco = 0 622.08 mbps cdr cid immunity ber 10 -10 (note 2) > 100 bits cdr sinusoidal jitter tolerance f > f c ber 10 -10 (note 3) 0.3 0.7 ui p-p sdi to sdo jitter transfer (notes 4, 5) 0.1 db downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications _______________________________________________________________________________________ 3 electrical characteristics (continued)(v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted. lvds outputs terminated 100 differential, cml inputs terminated 100 differential, cml outputs terminated 100 differential.) (note 1) parameter symbol conditions min typ max units sdi to sdo jitter transfer bandwidth (notes 3, 4) f c mhz parallel clock output random jitter (note 6) < 0.5 mui rms parallel-output clock to data time t ck-q figure 1 -80 +80 ps parallel clock and data-output rise/fall time t r , t f 20% to 80% 300 ps parallel-clock output duty cycle 45 55 % parallel-clock output frequency see table 2 mhz parallel-data output channel-to-channel skew 100 ps cdr acquisition time (after startup) 2 ms reference-output clock frequency see table 2 mhz serializer specifications parallel-input clock frequency see table 2 mhz serial-output data rate see table 2 mbps parallel-data input-setup time t su figure 1 170 ps parallel-data input-hold time t hd figure 1 300 ps serial-data output rise/fall time t r , t f 20% to 80% 160 ps serial-data output random jitter (notes 5, 6) 4 mui rms serial-data output deterministic jitter (notes 2, 5) 47 mui p-p burst enable to serial data msb time t b-msb figure 2 -50 +50 ps minimum pulse width of fifo reset ui is pcko period 4 ui tolerated drift between pcki and pcko after fifo reset ui is pcko period 1 ui i/o specifications cml differential input voltage v in 200 1600 mv p-p cml input common-mode range v cc - 1.49 v cc - 1.32 v cc - v in /4 v downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 4 _______________________________________________________________________________________ note 1: with a 19.4400mhz smd at-strip crystal at rfck1 and rfck2. note 2: pattern is 16 x 2 7 - 1 prbs, 100 cids, 16 x 2 7 - 1 prbs inverted, 100 cids inverted. note 3: for 622mbps operation, f c = 500khz. for 1.244gbps operation, f c = 1mhz. for 2.488gbps operation, f c = 2mhz. note 4: jitter transfer from sdi to sdo, with parallel side looped back. defined as: note 5: guaranteed by design and characterization. note 6: for 2.488gbps operation, measurement bandwidth = 8khz to 20mhz.for 1.244gbps operation, measurement bandwidth = 4khz to 10mhz. for 622mbps operation, measurement bandwidth = 2khz to 5mhz. for 155mbps operation, measurement bandwidth = 0.5khz to 1.3mhz. jitter transfer jitter on upstream signal ui jitt = e er on downstream signal ui downstream bit rate up s stream bit rate ? ? ? ? ? ? ? ? electrical characteristics (continued)(v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted. lvds outputs terminated 100 differential, cml inputs terminated 100 differential, cml outputs terminated 100 differential.) (note 1) parameter symbol conditions min typ max units cml differential output 640 800 1000 mv p-p cml differential output resistance 80 100 120 lvds input voltage range 0 2400 mv lvds differential input range (note 5) 100 600 mv lvds differential input resistance 80 100 120 lvds output voltage high 1475 mv lvds output voltage low 925 mv lvds output differential voltage v od figure 3 250 400 mv lvds output offset voltage v os v os = (v out+ + v out- )/2, figure 3 1125 1275 mv lvds output change in v od | v od | between 0 and 1 25 mv lvds output change in v os | v os | between 0 and 1 25 mv lvds differential output resistance 80 100 140 lvcmos input voltage low v il 0.8 v lvcmos input voltage high v ih 2.0 v lvcmos input current v ih = v cc or v il = ground -10 +10 a three-state input current mvco input, v ih = v cc or v il = ground -50 +50 a lvcmos output voltage low v ol i ol = 100a 0.2 v lvcmos output voltage high v oh i oh = -100a v cc - 0.2 v downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications _______________________________________________________________________________________ 5 pdo_pcko (mddr = 0) pcko (mddr = 1) t ck-q min t ck-q max 1ui1ui pcki t hd t su pdi_ figure 1. parallel interface timing diagrams figure 3. definition of lvds output levels t b-msb min t b-msb max sdo beno pdi3 pdi2 pdi0 pdi1 pdi1 figure 2. burst-enable timing v v od v od +v od v od(p-p) = v out+ - v out- -v od v os r l = 100 lvds v out- v out+ single- ended output differential output 0v downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 6 _______________________________________________________________________________________ typical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.) 1.244gbps serial data output (mvco = 1, msym = 0) MAX3886 toc01 120ps/div 100mv/div 622mbps parallel data and clock output (mvco = 1, mddr = 0) MAX3886 toc02 500ps/div 200mv/div 622mbps parallel data and clock output (mvco = 1, mddr = 1) MAX3886 toc03 500ps/div 200mv/div 2.488gbps jitter tolerance MAX3886 toc04 jitter frequency (hz) sinusoidal jitter tolerance (ui p-p ) 1m 100k 0.1 1 10 100 0.01 10k 10m tolerance exceeds testequipment generation limit tolerance exceeds testequipment generation limit g.984 mask g.984 mask 1.244gbps jitter tolerance MAX3886 toc05 jitter frequency (hz) sinusoidal jitter tolerance (ui p-p ) 1m 100k 0.1 1 10 100 0.01 10k 10m tolerance exceeds testequipment generation limit tolerance exceeds testequipment generation limit g.984 mask g.984 mask 622mbps jitter tolerance MAX3886 toc06 jitter frequency (hz) sinusoidal jitter tolerance (ui p-p ) 1m 100k 0.1 1 10 100 0.01 10k 10m g.984 mask g.983 mask tolerance exceeds testequipment generation limit tolerance exceeds testequipment generation limit sdi to sdo jitter transfer (sdi = 2.488gbps) MAX3886 toc07 jitter frequency (hz) jitter transfer (db) 1m 100k 10k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 -10 1k 10m g.984 mask g.984 mask sdi to sdo jitter transfer (sdi = 1.244gbps) MAX3886 toc08 jitter frequency (hz) jitter transfer (db) 1m 100k 10k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 -10 1k 10m g.984 mask g.984 mask sdi to sdo jitter transfer (sdi = 622mbps) MAX3886 toc09 jitter frequency (hz) jitter transfer (db) 1m 100k 10k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 -10 1k 10m g.984 mask g.983 mask downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications _______________________________________________________________________________________ 7 parallel clock output random jitter vs. temperature MAX3886 toc10 temperature ( c) random jitter (mui rms ) 60 35 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00.0 -40 85 sdi = 2.488gbps bw = 8khz to 20mhz sdi = 2.488gbps bw = 8khz to 20mhz sdi = 1.244gbps bw = 4khz to 10mhz sdi = 1.244gbps bw = 4khz to 10mhz sdi = 622gbps bw = 2khz to 5mhz sdi = 622mbps bw = 2khz to 5mhz sdo random jitter vs. temperature (symmetric, msym = 1) MAX3886 toc11 temperature ( c) random jitter (mui rms ) 60 35 -15 10 0.5 1.0 1.5 2.0 3.02.5 3.5 4.00.0 -40 85 sdi = 2.488gbps bw = 8khz to 20mhz sdo = 2.488gbps bw = 8khz to 20mhz sdi = 1.244gbps bw = 4khz to 10mhz sdo = 1.244gbps bw = 4khz to 10mhz sdi = 622gbps bw = 2khz to 5mhz sdo = 622mbps bw = 2khz to 5mhz sdo random jitter vs. temperature (asymmetric, msym = 0) MAX3886 toc12 temperature ( c) random jitter (mui rms ) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.00.0 -40 85 sdi = 2.488gbps bw = 8khz to 20mhz sdo = 1.244gbps bw = 4khz to 10mhz sdi = 622gbps bw = 2khz to 5mhz sdo = 155mbps bw = 0.5khz to 1.3mhz sdi = 1.244gbps bw = 4khz to 10mhz sdo = 622mbps bw = 2khz to 5mhz typical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.) pin description pin name function 1, 14, 15, 29, 42, 43, 56 gnd supply ground 2 tp1 test pin, reserved. connect to gnd for normal operation. 3, 6, 12, 28, 46, 53 v cc +3.3v supply voltage 4 sdi+ positive serial data input, cml or lvpecl 5 sdi- negative serial data input, cml or lvpecl 7 beno- negative burst-enable output, cml 8 beno+ positive burst-enable output, cml 9 tp2 test pin, reserved. connect to v cc for normal operation. 10 sdo- negative serial data output, cml 11 sdo+ positive serial data output, cml 13 tp3 test pin, reserved. connect to gnd for normal operation. 16 pcki+ positive parallel clock input, lvds 17 pcki- negative parallel clock input, lvds 18 pdi3+ positive parallel data input 3, lvds, msb (first serial bit out) 19 pdi3- negative parallel data input 3, lvds, msb (first serial bit out) 20 pdi2+ positive parallel data input 2, lvds 21 pdi2- negative parallel data input 2, lvds 22 pdi1+ positive parallel data input 1, lvds downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 8 _______________________________________________________________________________________ pin description (continued) pin name function 23 pdi1- negative parallel data input 1, lvds 24 pdi0+ positive parallel data input 0, lvds, lsb (last serial bit o ut) 25 pdi0- negative parallel data input 0, lvds, lsb (last serial bit out) 26 beni+ positive burst enable input, lvds 27 beni- negative burst enable input, lvds 30 rcko+ positive parallel rate reference clock output, lvds 31 rcko- negative parallel rate reference clock output, lvds 32 pdo3+ positive parallel data output 3, lvds, msb (first serial bi t in) 33 pdo3- negative parallel data output 3, lvds, msb (first se rial bit in) 34 pdo2+ positive parallel data output 2, lvds 35 pdo2- negative parallel data output 2, lvds 36 pdo1+ positive parallel data output 1, lvds 37 pdo1- negative parallel data output 1, lvds 38 pdo0+ positive parallel data output 0, lvds, lsb (last serial bi t in) 39 pdo0- negative parallel data output 0, lvds, lsb (last serial bit i n) 40 pcko+ positive parallel clock output, lvds; rate/4 or rate/8, depending on value of mddr pin. see figure 1 for timing diagram. 41 pcko- negative parallel clock output, lvds; rate/4 or rate/8, depending on value of mddr pin. see figure 1 for timing diagram. 44 ferr fifo error output, lvcmos. a high output indicates when the fifo r ead and write clocks attempt to access the same register. normally connected to mac ic. 45 frst fifo reset input, lvcmos. a high input resets the fifo. normally con nected to mac ic. 47 rfck2 reference clock crystal input. a 19.4400mhz crystal must be connected be tween rfck1 and rfck2; or a 19.4400mhz lvcmos clock source (capable of driving up to 10pf load) can be connected through a 10pf 10% series capacitor to rfck1, rfck2 unconnected. 48 rfck1 reference clock crystal input. see pin 47. 49 mddr dual data rate select input, lvcmos. a high input selects dual data rate (ddr) parallel clock output. see figure 1 for timing diagram. 50 msym symmetric select input, lvcmos. a high input selects symmet ric operation, a low input selects asymmetric operation. see table 2. 51 mvco vco rate select input, three-state. see table 2. 52 lock pll lock detector output, lvcmos. a high output indicates the p ll is in lock, this output can chatter when no valid input signal is present. 54 cfil pll filter capacitor connection. connect a 0.27f ceramic capacitor ( 10%, 10v, x7r-type) between pin 54 and pin 53. 55 tp4 test pin, reserved. connect to v cc for normal operation. ep exposed paddle. connect to thermal and electrical ground. downloaded from: http:///
detailed description the MAX3886 cdr/serdes provides 2.488gbps/1.244gbps/622mbps clock and data recovery, plus 1:4 deserializer for continuous downstream data and 1:4 serializer for burst upstream data (figure 4). specifically designed for gpon and bpon ont appli- cations, the serializer uses the recovered downstream clock to serialize the upstream serial data (loop-timed serialization). the upstream rate can be configured to be either equal to the downstream rate (symmetric operation) or a submultiple of the downstream rate (asymmetric operation). a low-cost 19.4400mhz smd- type crystal or external lvcmos source serves as the cdr frequency reference, providing robust frequency acquisition and lock detection. a parallel rate reference clock output, derived from the recovered downstream signal, is provided for use by the mac layer ic, and an integrated fifo is provided to deal with phase variation between the serializer and mac layer ic. once the fifo has been initialized, the serializer tolerates up to one parallel ui phase differ- ence between the read and write clocks. the fifo cir- cuitry includes an error output that indicates when the fifo attempts to read and write from the same location. an integrated burst-enable signal path also includes the fifo to simplify upstream burst timing. the deserializer parallel output clock can optionally be configured for dual data rate (ddr) operation. the high-speed cml-format serial-data interfaces are com- patible with maxim burst-mode laser drivers and both cml and lvpecl limiting amplifiers. the parallel data interfaces are lvds format for compatibility with fpgas or asics. serial input clock/data recovery clock and data recovery is provided by a phase-lockedloop (pll) with selectable 2.488ghz/1.244ghz/ 622mhz operation. the operating frequency is con- trolled by the three-state mvco input. a phase detector and filter generate error voltage proportional to the phase difference between the internal vco and the input data, and feedback in the pll drives the error voltage to zero, aligning the recovered clock to the center of the input data for retiming. a frequency detector assists the pll to ?ull in?to the serial data and generates the lock indicator signal on the lock pin. when no valid input signal is present, the lock output can oscillate (chatter) as the pll hunts for the input signal. the pll vco and integrated loop filter implement a second-order transfer function, with loop bandwidth dependent on the vco rate selected (e.g., 1.5mhz for 2.488gbps). an external filter capacitor, connectedbetween cfil and v cc sets the damping factor of the pll. all jitter specifications are based on an external0.27? capacitor. modifying the value of cfil changes jitter peaking, acquisition time, and loop stability but not loop bandwidth. pll reference clock oscillator an integrated oscillator provides a reference clock sig-nal for robust cdr acquisition and lock detection. this oscillator requires a 19.4400mhz crystal connected between rfck1 and rfck2, or an external lvcmos 19.4400mhz clock source can be used. see the applications information section for important informa- tion about crystal selection and how to connect anexternal clock source. deserializer and parallel output the downstream data is deserialized, producing fourparallel lvds outputs, pdo[3:0]? the first serial data bit received on the sdi input is the most significant bit (msb), which is routed to the parallel output pdo3. the lvds parallel output clock, pcko, can be configured for either full rate or half rate operation, as shown in the timing diagrams of figure 1. the pcko rate is con- trolled using the lvcmos mddr input. set the mddr pin to logic high to clock out parallel data on each edge of the pcko clock. parallel input, fifo, and serializer parallel data presented at the four lvds data inputs pdi[3:0] is latched into the input register using the lvds parallel input clock pcki and clocked out of the ont serdes using the recovered serial clock. the par- allel data bit pdi3 is the msb and the first bit out of the serial sdo output. for gpon and bpon ont applica- tions, the clock multiplier unit (cmu) frequency synthe- sizer normally incorporated in sonet serializers is eliminated, improving pon performance. asymmetric operation is configured using the lvcmos msym input (see table 2). the parallel clock is also output on the lvds rcko pins for use, if needed, by the mac layer. the serializer? 4-bit-long fifo accommodates phase variation between rcko and pcki. pcki provides the fifo write clock and the internal rcko is the read clock (loading the 4:1 serializer); this arrangement allows the phase relationship between these two clocks to vary ?ui. in the event that valid read and write clocks attempt to access the same fifo address, this error condition is indicated on the lvcmos ferr out- put. to initiate the fifo or clear an error condition, the lvcmos frst input must be asserted high for at least 4ui while valid clocks are present. MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications _______________________________________________________________________________________ 9 downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 10 ______________________________________________________________________________________ sdi+ sdi- freq detect cdr pll osc rfck1rfck2 lock cfil mvco d clk clk/4 4-bit serial to parallel div 2 pcko+pcko- mddr register pcki+pcki- 5 x 4 fifo 10 rcko+ msym q dd d d 4-bit parallel to serial wr sdo+ rcko- sdo- beno+ beno- rd ferrfrst clk clk 10 div 4 q pdo3+pdo3- lvds q pdo2+pdo2- lvds q pdo1+pdo1- lvds q pdo0+pdo0- lvds lvds lvds pdi3+pdi3- lvds pdi2+pdi2- lvds pdi1+pdi1- lvds pdi0+pdi0- lvds beni+beni- lvds cmos cmos cmos cmos dd q clk vco lpf pd cml cmos cmos div 2, div 4 lvds cml q clk cml MAX3886 figure 4. functional diagram downloaded from: http:///
burst-enable signal processing to minimize pon overhead, it is important that the laserdriver burst-enable (ben) signal correspond accurately with the beginning of the serial data burst. this is sup- ported in the MAX3886 by the beni lvds input and associated signal path. the lvds burst-enable signal from the mac layer ic is passed through the same fifo as the parallel data and output on the beno cml out- put, which ensures that the laser driver? burst enable matches the beginning of the associated serial msb. if frst or ferr are high, the beno output is forced low to prevent the laser driver from transmitting erroneous data. the parallel data setup and hold timing require- ments also apply to the burst-enable signal. lock detector output the lock detector operates by comparing a divided-down version of the vco output to the reference clock. the lock output pin indicates lock (high) when the fre- quency difference between the reference clock and the cdr vco is less than 250ppm, within the ?ullin?range of the pll. the lock output indicates out-of-lock (low) when the frequency difference between the reference clock and the cdr vco becomes more than 500ppm. when valid input data is present, this provides a stable lock indication. at power-up, the cdr takes approximately 50ms (ifvalid nrz data is present) for initial acquisition while the internal reference oscillator, the pll, and the fre- quency detector reach their operating conditions. during this startup period, the lock status output may provide false indication of a lock condition. once the pll and frequency detector are initialized, the nominal time for reacquisition of an nrz input is 2ms. when valid nrz input data is not present, the lock detector may produce a chattering lock indicator out- put while the pll searches for the input frequency. if needed, an external digital filter can be used to mask this chattering. table 1. lock detector output control input summary table 2 summarizes the clock and data rates as con-trolled by mvco, msym, and mddr. MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications ______________________________________________________________________________________ 11 cdr input lock output valid nrz data 1 no cdr input 0/1 (chatter) table 2. clock and data rate controls rx tx mvco msym mddr sdi rate (mbps) pdo rate (mbps) pcko (mhz) sdo rate (mbps) pdi rate (mbps) pcki (mhz) rcko (mhz) 0 0 0 622 155 155 155 39 39 39 0 0 1 622 155 78 155 39 39 39 0 1 0 622 155 155 622 155 155 155 0 1 1 622 155 78 622 155 155 155 open 0 0 1244 311 311 622 155 155 155 open 0 1 1244 311 155 622 155 155 155 open 1 0 1244 311 311 1244 311 311 311 open 1 1 1244 311 155 1244 311 311 311 1 0 0 2488 622 622 1244 311 311 311 1 0 1 2488 622 311 1244 311 311 311 1 1 0 2488 622 622 2488 622 622 622 1 1 1 2488 622 311 2488 622 622 622 downloaded from: http:///
MAX3886 applications information interfacing to the cdr/serdes the MAX3886 has cml, lvds, and lvcmos inputsand outputs. the high-speed cml (lvpecl-compati- ble) inputs, sdi? are biased to v cc - 1.3v with an on- chip high-impedance network (figure 5). figures 6 and7 provide examples of dc-coupled and ac-coupled termination networks that can be used to connect the limiting amplifier outputs (cml or lvpecl) to the sdi inputs. the two high-speed cml outputs, sdo and beno? have internal 50 back terminations to v cc (figure 8) and should be terminated with 50 to v cc or 100 differential at the laser driver inputs (figure 9). the burst sdo and beno outputs must be dc-coupledto the laser driver for proper operation. sdo can be ac-coupled if a continuous serial signal is provided between bursts (with gating provided by the laser dri- ver ben input). the lvds outputs (pdo[3:0]? pcko? rcko? require 100 differential termination for proper opera- tion. the lvds inputs (pdi[3:0]? pcki? are internallyterminated with 100 differential resistance, eliminating the need for external termination when connected to anlvds output (figure 10). equivalent circuits for the three-state input (mvco), lvcmos inputs (msym, mddr, frst), and lvcmos outputs (lock, ferr) are given in figure 11, figure 12,and figure 13. for more information on interfacing to maxim? high-speed i/o circuits, refer to application note hfan-01.0: introduction to lvds, pecl, and cml . multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 12 ______________________________________________________________________________________ MAX3886 v cc v cc 5k 16k 24k sdi+ v cc 5k sdi- v cc figure 5. cml (lvpecl-compatible) input 100 cml MAX3886 sdi+ dc-coupled limiting amplifier z 0 = 50 sdi- z 0 = 50 100 cml MAX3886 sdi+ ac-coupled 0.1 f limiting amplifier z 0 = 50 sdi- z 0 = 50 0.1 f figure 6. interface to limiting amplifier (cml outputs) downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications ______________________________________________________________________________________ 13 130 130 82 82 lvpecl MAX3886 sdi+ dc-coupled v cc limiting amplifier z 0 = 50 sdi- z 0 = 50 100 0.1 f 0.1 f lvpecl MAX3886 sdi+ ac-coupled limiting amplifier z 0 = 50 sdi- z 0 = 50 143 143 figure 7. interface to limiting amplifier (lvpecl outputs) 50 50 MAX3886 sdo+/beno+ sdo-/beno- v cc figure 8. cml outputs downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 14 ______________________________________________________________________________________ 100 cml in+ z 0 = 50 in- z 0 = 50 sdo+ sdo- 100 cml ben+ z 0 = 50 ben- z 0 = 50 beno+ beno- max3656/max3643 burst-mode laser driver MAX3886 cdr/serdes figure 9. interface to laser driver 100 z 0 = 50 z 0 = 50 100 100 100 z 0 = 50 z 0 = 50 mac ic MAX3886 lvds lvds lvds lvds figure 10. lvds interface downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications ______________________________________________________________________________________ 15 fifo control signals a valid input at frst is required to initialize the fifoafter the relationship between pcko or rcko and pcki has stabilized prior to operating the serializer, or after the ferr output has indicated that the fifo has overflowed or underflowed due to the phase difference between pcko or rcko and pcki exceeding its capacity. the mac ic provides the control signal for frst. ferr should not be directly connected to frst. if the pcki signal is interrupted between bursts, the fifo must be reset before the beginning of each burst while valid clocks are present. if a continuous pcki sig- nal is provided between bursts, the fifo maintains the correct fifo counter values as long as the phase rela- tionship does not change. reference clock oscillator the integrated reference oscillator requires a parallelresonant 19.4400mhz at-strip cut crystal connected between pins rfck1 and rfck2. it has 18pf nominal (15pf to 21pf) of on-chip crystal load capacitance; any frequency error due to mismatch to the rated crystal load capacitance must be included in the budget for the difference between reference clock frequency and input data rate. take care that the wiring capacitances at the nodes rfck1 and rfck2 are controlled (typical- ly no more than 2pf) to ensure proper operation. to drive the reference clock with an external 19.4400mhz lvcmos clock source, connect it to rfck1 through a 10pf ?0% series capacitor and leave rfck2 open. the lvcmos clock source must be capable of driving a 10pf load. to ensure proper acquisition, the maximum difference between the downstream data rate (divided down to 19.4400mhz) and 19.4400mhz clock should be 500ppm, including 57ppm required by the cdr itself. table 3 shows a typical budget. table 3. typical frequency budget MAX3886 v cc v cc mvco p n figure 11. three-state input (mvco) MAX3886 v cc v cc msym mddr frst p n figure 12. lvcmos inputs MAX3886 v cc v cc lockferr p n figure 13. lvcmos outputs description f (ppm) notes downstream data rate 50 g.983, g.984 crystal load capacitance 63 e.g., 21ppm/pf from 18pf crystal tolerance 75 crystal temperature stability 100 crystal aging 50 cdr operation 57 total 395 total is less than 500ppm downloaded from: http:///
MAX3886 power supply and ground connection the MAX3886 has six v cc connection pads, and instal- lation of a bypass capacitor at each v cc pad is recom- mended. all six v cc connections should be driven from the same source to eliminate the possibility of indepen-dent power-supply sequencing. pin 53 provides current directly to the internal vco stage; excessive supply noise at this node can result in increased jitter. the 56-pin tqfn package features an exposed pad(ep) that provides a low resistance thermal path for heat removal from the ic and must be connected to the circuit board ground plane for proper operation. the ep also provides essential electrical ground connectivity. multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications 16 ______________________________________________________________________________________ top view MAX3886 thin qfn (8mm 8mm 0.8mm) 15 1716 18 19 20 21 22 23 24 25 26 27 28 gnd pcki+ pcki- pdi3+ pdi3- pdi2+ pdi2- pdi1+ pdi1- pdi0+ pdi0- beni+ beni- v cc gnd tp4 cfil v cc lock mvco msym mddr rfck1 rfck2 v cc frst ferr gnd 48 47 46 45 44 4354 5356 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v cc tp3 gnd sdo+ sdo- tp2 beno+ beno- v cc sdi- sdi+ v cc tp1 gnd rcko-rcko+ gnd pdo3+ pdo3- pdo2+ pdo2- pdo1+ pdo1- pdo0+ pdo0- pcko+ pcko- gnd + ep* * the exposed pad of the thin qfn package must be soldered to ground for properthermal and electrical operation. pin configuration downloaded from: http:///
MAX3886 multirate cdr with integrated serializer/deserializer for gpon and bpon ont applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. chip information transistor count: 10,684process: sige bicmos package information (for the latest package outline information, go to www.maxim-ic.com/packages .) package type document no. 56 thin qfn 21-0135 downloaded from: http:///

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